1. Field of the Invention
Embodiments of the present invention relate generally to memory devices and more specifically to the processing of signals in high speed memory arrays.
2. Description of the Related Art
Electronic systems and devices, such as computers, personal organizers, cell phones, portable audio players, etc., typically include one or more memory devices to provide storage capability for the system. System memory is generally provided in the form of one or more integrated circuit chips and generally includes both random access memory (RAM) and read-only memory (ROM). System RAM is typically large and volatile and provides the system's main memory. Synchronous Dynamic RAM (SDRAM) is a commonly employed type of random access memory.
As will be appreciated, there are a number of different types of SDRAM devices. Early generation SDRAM devices are generally configured such that data from the memory cells may be accessed and one bit of data may be output on every clock cycle. Demands for higher processing speeds led to the development of Double Data Rate (DDR) SDRAM devices. DDR SDRAM devices generally allow for two bits of data to be accessed and output on every clock cycle. To achieve this, DDR SDRAM devices commonly clock data out on every rising and every falling edge of the clock signal. For example, with a clock frequency of 100 MHz, an SDRAM will transfer data on every rising edge of the clock pulse, thus achieving an effective 100 MHz transfer rate, or 10 ns to complete one clock cycle (also referred to as tck). DDR SDRAM will transfer data on every rising and falling edge of the clock, achieving an effective rate of 200 MHz with the same clock frequency.
Faster types of SDRAM include DDR2 SDRAM and DDR3 SDRAM. The advantage of DDR2 and DDR3 SDRAM over previous generations is the ability to run at even higher clock speeds due to an improved electrical interface, thus reducing the time required for a clock cycle. For example, DDR SDRAM generally allows for data to be transferred from the memory device at an effective clock rate of 200 to 550 MHz, or about 5 ns for one clock cycle (tck=5 ns). DDR2 SDRAM allows for data transfer around 400-1066 MHz, or about 3 ns for one clock cycle (tck=3 ns), while DDR3 SDRAM allows for effective data transfer of 800-1600 MHz, or about 1.5 ns for one clock cycle. (tck=1.5 ns). Faster versions of DDR3 SDRAM or further generations of SDRAM may be under 1 ns for one clock cycle. DDR2 and DDR3 SDRAM clock frequency is further boosted by other enhancements, such as larger pre-fetch buffers. With the increasing speeds, internal transfer of data within the memory device becomes increasingly difficult to manage.
During operation of these types of SDRAM, an activate (or active) command may be sent to the memory array. An activate command activates a row of the memory array. In some cases, one may have to wait multiple clock cycles before another activate command can be executed, thus the timing of the activate command signal may be important. Further, an internal bank address signal (also referred to as bank info signal or bank signal) should also be aligned with the activate signal, so that both signals are “high” at the same time. Typically, such alignment problems are resolved through the introduction of a clock signal to latch the various command signals. However, the addition of a latch clock signal adds to the logic and layout of the circuits that process the signals, and also requires tuning of the clock signal with the various command signals.
Embodiments of the present invention may be directed to one or more of the problems set forth above.